A flash memory device includes electrically erasable and programmable memory cells. The memory cells are composed of floating gate transistors. A floating gate transistor generally includes source and drain regions formed in a substrate, a floating gate on a channel region disposed between the source and drain regions, a control gate on the floating gate and an insulating layer between the floating gate and the control gate. The electrically erasable and programmable memory cells of the flash memory device may be programmed by hot electron injection to an OFF state. The programmed memory cells may be erased by tunneling to an ON state. As is also well known, flash memory devices may be classified into NAND and NOR type devices.
A flash memory device, such as a NOR type flash memory device, generally employs a sense amplifier in order to sense whether a memory cell is in an ON state or an OFF state. FIG. 1 is a circuit diagram of a conventional flash memory device 100 including a sense amplifier.
Referring to FIG. 1, the flash memory device 100 includes a memory cell 110 connected to a bit line B/L, a column select circuit 120 connected between the bit line B/L and a data line D/L, and a sense amplifier 130 connected to the data line D/L. The memory cell 110 is connected between the bit line B/L and a ground voltage source VSS and configured in the form of a floating gate transistor having a control gate connected to a word line W/L. The column select circuit 120 connects the bit line B/L to the data line D/L in response to a column address decoding signal YA. It will be understood that FIG. 1 only illustrates a single memory cell 110, but, conventionally, a large number of flash memory cells are provided in an integrated circuit flash memory device.
The sense amplifier 130 includes a first inverter 131 receiving a sense amplifier enable signal SAE and outputting a bias signal BIAS, a first NMOS transistor 133 having a gate receiving the bias signal BIAS and a source connected to the data line D/L, a second NMOS transistor 135 having a drain receiving the bias signal BIAS and a gate connected to the data line D/L, a first PMOS transistor 137 having a source provided with a power supply voltage VCC, a gate receiving a precharge signal PRE, and a drain connected to a node NA corresponding to the drain of the NMOS transistor 133. The sense amplifier 130 also includes a second PMOS transistor 139 having a source provided with the power supply voltage VCC and a gate receiving the precharge signal PRE, a third NMOS transistor 141 having a source connected to the drain of the second PMOS transistor 139, a gate receiving the bias signal BIAS, and a drain connected to the data line D/L, and a second inverter 143 receiving a signal of the node NA and outputting a sense amplifier output signal SAOUT.
The operation of the sense amplifier 130 will be explained with reference to FIGS. 1 and 2. FIG. 2 is a timing diagram of the operation of the sense amplifier 130. Referring to FIGS. 1 and 2, the bias signal BIAS transitions to a logic high level when the sense amplifier enable signal SAE is enabled by transitioning to a logic low level, as shown at (a). The bias signal BIAS at a logic high level turns on the first and third NMOS transistors 133 and 141. When the precharge signal PRE is enabled by transitioning to a logic low level in a precharging operation, the first PMOS transistor 137 is turned on. Accordingly, the node NA, the data line D/L and the bit line B/L are precharged to a logic high level, as shown at (b). When the word line WL is enabled to a logic high level, the state of the memory cell 110, that is, whether the memory cell 100 is an ON cell or an OFF cell, is sensed by determining the voltage of the bit line B/L. The bit line B/L has a ground voltage when the memory cell 110 is an ON cell and the bit line B/L has a predetermined voltage, for example, 0.6V, when the memory cell 110 is an OFF cell.
A coupling effect wherein the node NA that is precharged to a logic high level in a precharging operation may increase the voltage of the bias signal BIAS. Accordingly, the voltage of the data line D/L and the voltage of the bit line B/L may also increase, as shown at (c). When the voltage of the data line D/L increases, the second NMOS transistor 135 is turned on to decrease the voltage of the bias signal BIAS, as shown at (d). Accordingly, the current flowing through the first and second NMOS transistors 133 and 141 may be reduced, and thus the voltage of the bit line B/L may not be sufficiently precharged.
When the memory cell 110 is an ON cell in the next sensing operation, the bit line B/L has a ground voltage VSS based on a turned on memory cell transistor, and thus the ON cell is correctly sensed. However, when the memory cell 110 is an OFF cell, the OFF cell may be sensed as an ON cell due to the voltage of the bit line B/L, which may not be sufficiently precharged.